[9.18] chg: dev: Use release memory ordering when incrementing reference counter

As the relaxed memory ordering doesn't ensure any memory
synchronization, it is possible that the increment will succeed even
in the case when it should not - there is a race between
atomic_fetch_sub(..., acq_rel) and atomic_fetch_add(..., relaxed).
Only the result is consistent, but the previous value for both calls
could be same when both calls are executed at the same time.

Backport of MR !9460

Merge branch 'backport-ondrej/use-release-memory-ordering-for-reference-counting-9.18' into 'bind-9.18'

See merge request isc-projects/bind9!9568
This commit is contained in:
Ondřej Surý
2024-10-02 07:09:23 +00:00

View File

@@ -79,7 +79,7 @@ isc_refcount_increment0(isc_refcount_t *target) {
#define isc_refcount_increment0(target) \
({ \
uint_fast32_t __v; \
__v = atomic_fetch_add_relaxed(target, 1); \
__v = atomic_fetch_add_release(target, 1); \
INSIST(__v < UINT32_MAX); \
__v; \
})
@@ -102,7 +102,7 @@ isc_refcount_increment(isc_refcount_t *target) {
#define isc_refcount_increment(target) \
({ \
uint_fast32_t __v; \
__v = atomic_fetch_add_relaxed(target, 1); \
__v = atomic_fetch_add_release(target, 1); \
INSIST(__v > 0 && __v < UINT32_MAX); \
__v; \
})