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[PR #15833] Add riscv64 support #77614

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opened 2026-05-05 10:17:13 -05:00 by GiteaMirror · 0 comments
GiteaMirror commented 2026-05-05 10:17:13 -05:00
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📋 Pull Request Information

Original PR: https://github.com/ollama/ollama/pull/15833
Author: @velonica0
Created: 4/27/2026
Status: 🔄 Open

Base: main ← Head: risc-v

📝 Commits (1)

📊 Changes

6 files changed (+2351 additions, -1 deletions)

View changed files

📝 CMakeLists.txt (+3 -1)
➕ ml/backend/ggml/ggml/src/ggml-cpu/arch/riscv/cpu-feats.cpp (+38 -0)
➕ ml/backend/ggml/ggml/src/ggml-cpu/arch/riscv/quants.c (+1956 -0)
➕ ml/backend/ggml/ggml/src/ggml-cpu/arch/riscv/repack.cpp (+342 -0)
➕ ml/backend/ggml/ggml/src/ggml-cpu/arch/riscv/riscv.go (+7 -0)
➕ ml/backend/ggml/ggml/src/ggml-cpu/cpu_riscv64.go (+5 -0)

📄 Description

Closes #8857

PR #6627 added baseline riscv64 support. This PR follows upstream llama.cpp’s per-architecture arch/* split by aligning Ollama’s vendored ggml RISC-V layout with the same vendored baseline (b7847), importing ggml-cpu/arch/riscv and adding the missing riscv64 Go/cgo wiring.

GGML_CPU_ALL_VARIANTS stays disabled on riscv64 for now because Ollama’s current vec.h does not yet match the vendored llama.cpp b7847 baseline, so the RVV path cannot be enabled cleanly. RVV support will be handled separately in #3911.

This has been tested on a SpacemiT K1 CPU and can run successfully.

🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.

## 📋 Pull Request Information **Original PR:** https://github.com/ollama/ollama/pull/15833 **Author:** [@velonica0](https://github.com/velonica0) **Created:** 4/27/2026 **Status:** 🔄 Open **Base:** `main` ← **Head:** `risc-v` --- ### 📝 Commits (1) - [`8b69ab2`](https://github.com/ollama/ollama/commit/8b69ab2347edebabc78efb52d8ce4f601017d6cb) add risc-v support ### 📊 Changes **6 files changed** (+2351 additions, -1 deletions) <details> <summary>View changed files</summary> 📝 `CMakeLists.txt` (+3 -1) ➕ `ml/backend/ggml/ggml/src/ggml-cpu/arch/riscv/cpu-feats.cpp` (+38 -0) ➕ `ml/backend/ggml/ggml/src/ggml-cpu/arch/riscv/quants.c` (+1956 -0) ➕ `ml/backend/ggml/ggml/src/ggml-cpu/arch/riscv/repack.cpp` (+342 -0) ➕ `ml/backend/ggml/ggml/src/ggml-cpu/arch/riscv/riscv.go` (+7 -0) ➕ `ml/backend/ggml/ggml/src/ggml-cpu/cpu_riscv64.go` (+5 -0) </details> ### 📄 Description Closes #8857 PR #6627 added baseline `riscv64` support. This PR follows upstream `llama.cpp`’s per-architecture `arch/*` split by aligning Ollama’s vendored ggml RISC-V layout with the same vendored baseline (`b7847`), importing `ggml-cpu/arch/riscv` and adding the missing `riscv64` Go/cgo wiring. `GGML_CPU_ALL_VARIANTS` stays disabled on `riscv64` for now because Ollama’s current `vec.h` does not yet match the vendored `llama.cpp` `b7847` baseline, so the RVV path cannot be enabled cleanly. RVV support will be handled separately in #3911. This has been tested on a SpacemiT K1 CPU and can run successfully. --- <sub>🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.</sub>
GiteaMirror added the pull-request label 2026-05-05 10:17:13 -05:00
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