- Move Figure 5 (design-space heatmap) to its first reference in 6.2 so the
section-boundary float barrier no longer flushes p24's left column.
- Tighten the abstract from 231 to ~175 words for cleaner progressive disclosure.
- Correct Validation Anchor 4: PaLM-540B ran on 6,144 TPU v4 chips (two pods),
57.8% HFU vs 46.2% MFU; drop the fabricated 64,000-chip scaling claim.
- Split the chain-of-thought latency multiplier (6.5x) from the cost/fleet
multiplier (~8x, tracking total decode tokens).
Replace the model_scaling raster in sustainable_ai with a matplotlib figure cell generated from published Kaplan et al. (2020) fit constants, now stored as Literature.KaplanScalingLaws with provenance so the figure traces to source-of-truth instead of a traced image.
Convert the remaining 'fig = plt.gcf()' figure cells across seven vol2 chapters (collective_communication, edge_intelligence, fleet_orchestration, ops_scale, performance_engineering, robust_ai, sustainable_ai) to end with plt.show() then plt.close(), matching the book's standard figure-cell convention so every generated figure is explicitly emitted and closed.
Three runnable Tier 1-3 examples extending the appendix cookbook, each with output verified verbatim against the current package and added to the cookbook reference list:
- Scenario F: Scenario.evaluate() three-level scorecard (Feasibility/Performance/Macro) via the pre-built ChatbotServing scenario.
- Scenario G: ParallelismOptimizer design-space search recovering TP=8/PP=2/DP=16 on a 256-GPU cluster with the ranked candidate list.
- Scenario H: a single Engine.solve call spanning datacenter to microcontroller (LeNet1 on ESP32-S3, MobileNet variants on Jetson Orin Nano and Coral).
paper.tex compiles (pdflatex); the only build errors in a fresh worktree are the untracked figure PDFs, which are present in the main checkout.
Audited paper.tex against the live package; the framework description (YAML+pydantic registries, 8 zoos, flop base dimension, instance/tech-class) was already accurate. Updated every drifted number/claim:
- Counts: 116 -> 126 provenance records; 34 -> 37 hardware devices (added V100 PCIe, Jetson Orin Nano, Apple M2 rows to the catalog table); 749 -> 862 test suite; figure caption four -> five invariant checks (matching the five enumerated in the Validation section).
- Executed-listing outputs regenerated from the current solvers: Solver Composition (54.9% / 68.1 day / 15,905,569 USD) and Carbon Accounting (57 days / 110.3 tonnes).
- Validation: Anchor 3 39.6 -> 39.1% MFU. Anchor 7 rewritten -- the ParallelismOptimizer now recovers Meta's TP=8, PP=16 backbone because the optimizer-state-aware memory prescreen (fixed in the mlsysim audit) drives PP=16 (was PP=4); prescreen prose now reads weights+gradients+optimizer state.
- validate_anchors.py: synced PAPER_CLAIMS/REPORTED to the corrected values; Anchor 5 now uses Chinchilla's actual C=5.88e23 (-> 70.0B). Harness reports all seven anchors match.
paper.tex compiles cleanly (pdflatex, no errors).
- ParallelismOptimizer: include Adam optimizer state in the per-GPU memory
prescreen (was weights + gradients only), so the search no longer admits
parallelism splits that OOM the instant optimizer state is allocated;
activations stay out (the search does not model the microbatch that sizes them)
- SystemEvaluator: the distributed feasibility lens reports SKIPPED with a
reason instead of a no-op PASS, so the scorecard never claims 'will run'
without having checked
- TopologyModel: reconcile the bisection-bandwidth comment with the tested
fat-tree-normalized beta convention (comment-only; value unchanged)
resolve_precision('fp32') yields key 'fp32', which was absent from the H100/H200 precision_flops map (stored as 'fp32_cuda' = 67 TFLOP/s), so Engine.solve fell through to peak_flops (989, the FP16 dense rate) -- a ~15x FP32 overestimate reachable by no precision string.
- Rename precision_flops key fp32_cuda -> fp32 on H100 and H200 (value 67 TFLOP/s unchanged)
- Propagate the rename to every consumer, value-preserving: 2 LEGO cells
(compute_infrastructure, appendix_assumptions), 2 mlsysim_constants audit
manifests, and the migrate-constants map
- Add test_hardware guards: precision-vocabulary check (no canonical precision
aliased away) + H100/H200 fp32 -> 67 regression
Add native Binder checks for LEGO formatting/unit/prose contracts, extend mlsysim formatter helpers, and normalize Vol1/Vol2 LEGO output strings through typed formatters.
Validate precision-sensitive prose rendering across both volumes and promote direct math/string assembly to fmt_math, fmt_display_math, fmt_text, and domain-specific helpers.
Adds an EdgeInferenceBenchmarks Python series (8 MLPerf-Tiny / vendor latency-
energy points across MCU/ASIC, edge-accelerator, and edge-GPU tiers) with
provenance, mirroring the ComputeTrend series pattern. @fig-edge-inference-landscape
now builds its device list from the registry instead of inline tuples.
Adds a Literature.ResponsibleAIOverhead collection (DP, fairness, SHAP, adversarial, federated overheads across accuracy/training/inference/memory) with RESPONSIBLE_AI_OVERHEAD provenance. The @tbl-responsible-ai-overhead cells now source their ranges from the registry instead of hardcoded values.
The 64-A100 training-emissions cells (TrainingEmissions, TrainingEmbodiedRecap)
read Hardware.Cloud.H100.embodied_carbon_kg (164) for an A100 run. Point them at
Hardware.Cloud.A100, and update the registry A100 value 130 -> 150 kg to match the
Luccioni et al. 2023 figure the chapter already cites. Registry, cells, and prose
now agree: 150 kg/A100, ~9.6 t unamortized, ~92 kg amortized for the 14-day run.
Adds a MigProfile schema + Hardware.Cloud.A100.mig_profiles (1g.10gb..7g.80gb,
GPU memory + SM count) sourced to the NVIDIA MIG User Guide. The A100-80GB MIG
profile table in fleet_orchestration (w1A-004) now pulls its GPU-memory and
SM-count cells from the registry instead of hardcoded values.
Adds Systems.Reliability.Hbm.soft_error_fit_per_mbit = 250 FIT/Mbit, sourced
to a new HBM_SOFT_ERROR_FIT_PER_MBIT provenance entry citing the published
200-5000 FIT/Mbit DRAM soft-error range (Tezzaron; soft-error literature). A
field validator guards that band so a units/transcription slip cannot land.
Pins fault_tolerance w1A-003: the unprotected-HBM soft-error budget (250 FIT/Mbit
x 1,024 x A100 HBM -> aggregate FIT -> ~20 s mean time to first corruption) now
flows from a HbmSerBudget LEGO cell instead of hardcoded prose literals.
Add VIDEO_4K_WIDTH/HEIGHT to mlsysim core/units.py and import them
(with VIDEO_BYTES_PER_PIXEL_RGB) into the DataLocalityInvariant LEGO
cell, matching the sibling BandwidthBottleneck cell that already pulls
1080p dimensions from the registry. Genuinely scenario-specific inputs
(broadband uplink, cloud latency, fps) stay local and documented.
Document the 4K parameters in the appendix scale-references table.
Rendered values unchanged (24.9 MB frame, 1990.7 ms vs 110 ms).
Hardware specs already get sanity-bounds protection in
test_physics_bounds.py (catching an 80 TB/s typo for 80 GB/s), but
registered model specs had no equivalent guard: a transposed parameter
count (124M typed as 421M) or a decimal slip (124 typed as 12.4) in a
registry YAML would bind silently.
Two layers now protect every TransformerWorkload:
- test_transformer_attention_geometry: universal invariant that
hidden_dim splits evenly into heads with a 32-256 head dim and is a
multiple of 64 (catches transposed hidden_dim/heads across all 13
registered transformers).
- test_transformer_curated_specs: a curated, web-verified spec table
(seeded with GPT-2 Small, Radford 2019) that fails CI when a registry
value diverges >1% from its verified figure. Extend the table whenever
a new model spec is registered.
Wire GPT2_Small into the two chapter-side checks so its specs cannot be
hardcoded into a LEGO cell: CANONICAL in audit_mlsysim_drift.py and
HARDCODED_REGISTRY in book_check_registry_sources.py.
Verified the guard fires: transposing 124M to 421M fails the curated
test, and swapping hidden_dim/heads fails the geometry invariant.
- swap hardcoded GPT-2 XL heads=25 to Models.Language.GPT2.heads
- add GPT2_Small (124M, 12 layers, 768 hidden, 12 heads) to the model
registry with Radford 2019 provenance; attention-intensity cell now sources
hidden_dim/heads from it (values identical, mlsysim suite 814 passed)
- Add full_examples field to DatasetProfile + Datasets.ImageNet (14,197,122,
web-verified vs Deng 2009) distinct from training_examples (ILSVRC-1k, 1.28M)
- Pin both 'ImageNet 14 million images' refs to ImageNetCorpus cell (now 14.2M from registry) (w1A-vol1-ml_workflow-005)
- Add Literature.Surveys group with the six CrowdFlower 2016 time-allocation
buckets (60/19/9/3/4/5), verified against the primary report (page 6 chart),
with provenance URL + new CROWDFLOWER_2016 key.
- DataScientistTime cell LOAD now reads buckets from Literature.Surveys instead of
hardcoding them; identical values, GUARD sum=100 holds. (w1A-vol1-ml_workflow-006)
Verified against Apple newsroom (June 6, 2022): 16-core Neural Engine = 15.8
trillion ops/sec, 100 GB/s unified memory. Provenance kind estimate -> datasheet
with official Apple URL. Value unchanged.
The 4.1 GFLOP value (modern MAC count, torchvision/fvcore ~4.09 GMAC) is the
book-wide figure (nn_architectures GFLOP guards, frameworks, roofline tutorial).
Provenance previously cited He et al. (2016) whose Table 1 reports 3.8e9 under
their counting; add a notes field documenting the convention so value and citation
no longer appear to contradict. Value unchanged.
NVIDIA quotes NVLink (and Google quotes TPU ICI) as bidirectional totals,
while PCIe and fabric entries store per-direction rates — two conventions
under one field name, undeclared. IOInterconnect now carries an explicit
direction field ('per_direction' default; 'bidirectional_total' tagged on
all NVLink/ICI YAML entries) and a bandwidth_per_direction accessor.
Systems.Nodes intra_node_bw now feeds the per-direction rate (H100 450,
A100 300, B200 900 GB/s) into the collective beta terms — previously the
bidirectional total made every intra-node-bound allreduce/TP latency ~2x
optimistic. Stored datasheet figures are unchanged, so spec displays keep
the familiar marketing numbers.
Distributed golden re-pinned to the corrected physics (tp comm 267->535 ms,
scaling efficiency 0.809->0.761 on the Llama3-8B/Research_256 case); new
convention test pins the tagging and accessor; drift auditor gains
per-direction entries.
Audit 2026-06-09, findings_provenance.md M1/M2. Ruling: VJ 2026-06-10.
