migrate t_atomic to lib/isc/tests/atomic_test
This commit is contained in:
Evan Hunt
332
lib/isc/tests/atomic_test.c
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332
lib/isc/tests/atomic_test.c
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/*
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* Copyright (C) Internet Systems Consortium, Inc. ("ISC")
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/.
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*
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* See the COPYRIGHT file distributed with this work for additional
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* information regarding copyright ownership.
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*/
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#include <config.h>
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#include <stdlib.h>
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#include <atf-c.h>
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#include <isc/atomic.h>
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#include <isc/result.h>
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#include "isctest.h"
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#define TASKS 32
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#define ITERATIONS 1000
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#define COUNTS_PER_ITERATION 1000
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#define INCREMENT_64 (isc_int64_t)0x0000000010000000
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#define EXPECTED_COUNT_32 (TASKS * ITERATIONS * COUNTS_PER_ITERATION)
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#define EXPECTED_COUNT_64 (TASKS * ITERATIONS * COUNTS_PER_ITERATION * INCREMENT_64)
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typedef struct {
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isc_uint32_t iteration;
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} counter_t;
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counter_t counters[TASKS];
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#if defined(ISC_PLATFORM_HAVEXADD)
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static isc_int32_t counter_32;
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static void
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do_xadd(isc_task_t *task, isc_event_t *ev) {
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counter_t *state = (counter_t *)ev->ev_arg;
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int i;
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for (i = 0 ; i < COUNTS_PER_ITERATION ; i++) {
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isc_atomic_xadd(&counter_32, 1);
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}
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state->iteration++;
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if (state->iteration < ITERATIONS) {
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isc_task_send(task, &ev);
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} else {
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isc_event_free(&ev);
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}
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}
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ATF_TC(atomic_xadd);
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ATF_TC_HEAD(atomic_xadd, tc) {
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atf_tc_set_md_var(tc, "descr", "atomic XADD");
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}
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ATF_TC_BODY(atomic_xadd, tc) {
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isc_result_t result;
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isc_task_t *tasks[TASKS];
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isc_event_t *event = NULL;
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int i;
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UNUSED(tc);
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result = isc_test_begin(NULL, ISC_TRUE);
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ATF_REQUIRE_EQ(result, ISC_R_SUCCESS);
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memset(counters, 0, sizeof(counters));
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counter_32 = 0;
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/*
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* Create our tasks, and allocate an event to get the counters going.
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*/
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for (i = 0 ; i < TASKS ; i++) {
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tasks[i] = NULL;
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ATF_REQUIRE_EQ(isc_task_create(taskmgr, 0, &tasks[i]),
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ISC_R_SUCCESS);
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event = isc_event_allocate(mctx, NULL, 1000, do_xadd,
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&counters[i],
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sizeof(struct isc_event));
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ATF_REQUIRE(event != NULL);
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isc_task_sendanddetach(&tasks[i], &event);
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}
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isc_test_end();
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printf("32-bit counter %d, expected %d\n",
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counter_32, EXPECTED_COUNT_32);
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ATF_CHECK_EQ(counter_32, EXPECTED_COUNT_32);
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counter_32 = 0;
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}
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#endif
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#if defined(ISC_PLATFORM_HAVEXADDQ)
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static isc_int64_t counter_64;
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static void
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do_xaddq(isc_task_t *task, isc_event_t *ev) {
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counter_t *state = (counter_t *)ev->ev_arg;
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int i;
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for (i = 0 ; i < COUNTS_PER_ITERATION ; i++) {
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isc_atomic_xaddq(&counter_64, INCREMENT_64);
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}
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state->iteration++;
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if (state->iteration < ITERATIONS) {
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isc_task_send(task, &ev);
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} else {
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isc_event_free(&ev);
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}
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}
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ATF_TC(atomic_xaddq);
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ATF_TC_HEAD(atomic_xaddq, tc) {
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atf_tc_set_md_var(tc, "descr", "atomic XADDQ");
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}
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ATF_TC_BODY(atomic_xaddq, tc) {
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isc_result_t result;
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isc_task_t *tasks[TASKS];
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isc_event_t *event = NULL;
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int i;
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UNUSED(tc);
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result = isc_test_begin(NULL, ISC_TRUE);
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ATF_REQUIRE_EQ(result, ISC_R_SUCCESS);
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memset(counters, 0, sizeof(counters));
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counter_64 = 0;
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/*
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* Create our tasks, and allocate an event to get the counters going.
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*/
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for (i = 0 ; i < TASKS ; i++) {
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tasks[i] = NULL;
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ATF_REQUIRE_EQ(isc_task_create(taskmgr, 0, &tasks[i]),
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ISC_R_SUCCESS);
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event = isc_event_allocate(mctx, NULL, 1000, do_xaddq,
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&counters[i],
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sizeof(struct isc_event));
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ATF_REQUIRE(event != NULL);
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isc_task_sendanddetach(&tasks[i], &event);
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}
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isc_test_end();
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printf("64-bit counter %"ISC_PRINT_QUADFORMAT"d, "
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"expected %"ISC_PRINT_QUADFORMAT"d\n",
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counter_64, EXPECTED_COUNT_64);
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ATF_CHECK_EQ(counter_64, EXPECTED_COUNT_64);
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counter_32 = 0;
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}
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#endif
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#if defined(ISC_PLATFORM_HAVEATOMICSTORE)
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static isc_int32_t store_32;
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static void
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do_store(isc_task_t *task, isc_event_t *ev) {
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counter_t *state = (counter_t *)ev->ev_arg;
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int i;
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isc_uint32_t r;
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isc_uint32_t val;
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r = random() % 256;
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val = (r << 24) | (r << 16) | (r << 8) | r;
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for (i = 0 ; i < COUNTS_PER_ITERATION ; i++) {
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isc_atomic_store(&store_32, val);
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}
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state->iteration++;
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if (state->iteration < ITERATIONS) {
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isc_task_send(task, &ev);
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} else {
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isc_event_free(&ev);
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}
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}
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ATF_TC(atomic_store);
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ATF_TC_HEAD(atomic_store, tc) {
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atf_tc_set_md_var(tc, "descr", "atomic STORE");
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}
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ATF_TC_BODY(atomic_store, tc) {
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isc_result_t result;
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isc_task_t *tasks[TASKS];
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isc_event_t *event = NULL;
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isc_uint32_t val;
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isc_uint32_t r;
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int i;
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UNUSED(tc);
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result = isc_test_begin(NULL, ISC_TRUE);
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ATF_REQUIRE_EQ(result, ISC_R_SUCCESS);
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memset(counters, 0, sizeof(counters));
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store_32 = 0;
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/*
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* Create our tasks, and allocate an event to get the counters
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* going.
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*/
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for (i = 0 ; i < TASKS ; i++) {
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tasks[i] = NULL;
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ATF_REQUIRE_EQ(isc_task_create(taskmgr, 0, &tasks[i]),
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ISC_R_SUCCESS);
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event = isc_event_allocate(mctx, NULL, 1000, do_store,
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&counters[i],
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sizeof(struct isc_event));
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ATF_REQUIRE(event != NULL);
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isc_task_sendanddetach(&tasks[i], &event);
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}
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isc_test_end();
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r = store_32 & 0xff;
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val = (r << 24) | (r << 16) | (r << 8) | r;
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printf("32-bit store 0x%x, expected 0x%x\n",
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(isc_uint32_t) store_32, val);
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ATF_CHECK_EQ((isc_uint32_t) store_32, val);
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store_32 = 0;
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}
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#endif
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#if defined(ISC_PLATFORM_HAVEATOMICSTOREQ)
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static isc_int64_t store_64;
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static void
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do_storeq(isc_task_t *task, isc_event_t *ev) {
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counter_t *state = (counter_t *)ev->ev_arg;
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int i;
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isc_uint8_t r;
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isc_uint64_t val;
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r = random() % 256;
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val = (((isc_uint64_t) r << 24) |
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((isc_uint64_t) r << 16) |
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((isc_uint64_t) r << 8) |
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(isc_uint64_t) r);
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val |= ((isc_uint64_t) val << 32);
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for (i = 0 ; i < COUNTS_PER_ITERATION ; i++) {
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isc_atomic_storeq(&store_64, val);
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}
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state->iteration++;
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if (state->iteration < ITERATIONS) {
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isc_task_send(task, &ev);
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} else {
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isc_event_free(&ev);
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}
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}
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ATF_TC(atomic_storeq);
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ATF_TC_HEAD(atomic_storeq, tc) {
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atf_tc_set_md_var(tc, "descr", "atomic STOREQ");
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}
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ATF_TC_BODY(atomic_storeq, tc) {
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isc_result_t result;
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isc_task_t *tasks[TASKS];
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isc_event_t *event = NULL;
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isc_uint64_t val;
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isc_uint32_t r;
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int i;
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UNUSED(tc);
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result = isc_test_begin(NULL, ISC_TRUE);
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ATF_REQUIRE_EQ(result, ISC_R_SUCCESS);
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memset(counters, 0, sizeof(counters));
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store_64 = 0;
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/*
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* Create our tasks, and allocate an event to get the counters
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* going.
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*/
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for (i = 0 ; i < TASKS ; i++) {
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tasks[i] = NULL;
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ATF_REQUIRE_EQ(isc_task_create(taskmgr, 0, &tasks[i]),
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ISC_R_SUCCESS);
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event = isc_event_allocate(mctx, NULL, 1000, do_storeq,
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&counters[i],
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sizeof(struct isc_event));
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ATF_REQUIRE(event != NULL);
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isc_task_sendanddetach(&tasks[i], &event);
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}
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isc_test_end();
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r = store_64 & 0xff;
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val = (((isc_uint64_t) r << 24) |
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((isc_uint64_t) r << 16) |
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((isc_uint64_t) r << 8) |
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(isc_uint64_t) r);
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val |= ((isc_uint64_t) val << 32);
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printf("64-bit store 0x%"ISC_PRINT_QUADFORMAT"x, "
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"expected 0x%"ISC_PRINT_QUADFORMAT"x\n",
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(isc_uint64_t) store_64, val);
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ATF_CHECK_EQ((isc_uint64_t) store_64, val);
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store_64 = 0;
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}
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#endif
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/*
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* Main
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*/
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ATF_TP_ADD_TCS(tp) {
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#if defined(ISC_PLATFORM_HAVEXADD)
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ATF_TP_ADD_TC(tp, atomic_xadd);
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#endif
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#if defined(ISC_PLATFORM_HAVEXADDQ)
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ATF_TP_ADD_TC(tp, atomic_xaddq);
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#endif
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#ifdef ISC_PLATFORM_HAVEATOMICSTORE
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ATF_TP_ADD_TC(tp, atomic_store);
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#endif
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#if defined(ISC_PLATFORM_HAVEATOMICSTOREQ)
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ATF_TP_ADD_TC(tp, atomic_storeq);
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#endif
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return (atf_no_error());
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}
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